/*
 * Copyright (c) 2022, IMMORTA Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *
 * - Redistributions of source code must retain the above copyright notice, this list
 *   of conditions and the following disclaimer.
 *
 * - Redistributions in binary form must reproduce the above copyright notice, this
 *   list of conditions and the following disclaimer in the documentation and/or
 *   other materials provided with the distribution.
 *
 * - Neither the name of IMMORTA Inc. nor the names of its
 *   contributors may be used to endorse or promote products derived from this
 *   software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef MPU_REG_ACCESS_H
#define MPU_REG_ACCESS_H

/*!
 * @file mpu_reg_access.h
 * @brief This file declares or defines mpu register access functions
 */

/*******Includes***************************************************************/
#include "device_registers.h"
#include "mpu_drv.h"

/*******Definitions************************************************************/


/*******APIs*******************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
#if (__MPU_PRESENT == 1U)

/*!
 * @brief Enable the MPU
 *
 * @param[in] regBase: The MPU register base address
 * @param[in] MPU_Control: Specifies the control mode of the MPU during hard fault,
 *            NMI, FAULTMASK and privileged access to the default memory
 *            This parameter can be one of the following values:
 *            - MPU_HFNMI_PRIVDEF_NONE
 *            - MPU_HARDFAULT_NMI
 *            - MPU_PRIVILEGED_DEFAULT
 *            - MPU_HFNMI_PRIVDEF
 * @return None
 */
static inline void MPU_REG_Enable(MPU_Type* regBase, uint32_t mpuControl)
{
    /* Enable the MPU */
    regBase->CTRL = (mpuControl | MPU_CTRL_ENABLE_Msk);
    /* Ensure MPU setting take effects */
    __DSB();
    __ISB();
}


/*!
 * @brief Disable the MPU
 *
 * @param[in] regBase: The MPU register base address
 * @return None
 */
static inline void MPU_REG_Disable(MPU_Type* regBase)
{
    /* Make sure outstanding transfers are done */
    __DMB();
    /* Disable the MPU and clear the control register*/
    regBase->CTRL  = 0;
}


/*!
 * @brief Initialize and configure the Region and the memory to be protected
 *
 * @param[in] regBase: The MPU register base address
 * @param[in] regionConfig: Pointer to a mpu_region_config_t structure that contains
  *                         the initialization and configuration information
 * @return None
 */
static inline void MPU_REG_ConfigRegion(MPU_Type* regBase, mpu_region_config_t* regionConfig)
{
    /* Set the Region number */
    regBase->RNR = regionConfig->Number;
    regBase->RBAR = regionConfig->BaseAddress;
    regBase->RASR = ((uint32_t)regionConfig->DisableExec         << MPU_RASR_XN_Pos)    |
                    ((uint32_t)regionConfig->AccessPermission    << MPU_RASR_AP_Pos)    |
                    ((uint32_t)regionConfig->TypeExtField        << MPU_RASR_TEX_Pos)   |
                    ((uint32_t)regionConfig->IsShareable         << MPU_RASR_S_Pos)     |
                    ((uint32_t)regionConfig->IsCacheable         << MPU_RASR_C_Pos)     |
                    ((uint32_t)regionConfig->IsBufferable        << MPU_RASR_B_Pos)     |
                    ((uint32_t)regionConfig->SubRegionDisable    << MPU_RASR_SRD_Pos)   |
                    ((uint32_t)regionConfig->Size                << MPU_RASR_SIZE_Pos)  |
                    ((uint32_t)regionConfig->Enable              << MPU_RASR_ENABLE_Pos);
}
#endif /* __MPU_PRESENT */

#if defined(__cplusplus)
}
#endif

#endif /* MPU_REG_ACCESS_H */

/*******EOF********************************************************************/

